Aspects disclosed herein relate to processing systems which implement memory prefetching. More specifically, aspects disclosed herein relate to intelligent data prefetching using address delta prediction.
Prefetching is an optimization used in many processors. Data prefetching attempts to speed up the execution of memory operations by predicting which data is expected to be referenced by a memory operation and prefetching the predicted data into a hardware cache. In this way, the memory operation can execute much faster, rather than waiting for a miss in the cache and incurring the delay to bring the data from main memory and/or higher-level caches.
Some conventional prefetchers, such as a stride prefetcher, attempt to identify a pattern (a stride) in the memory references generated by one or more memory operations that access the same memory region. However, these prefetchers identify such patterns in contiguous memory regions. Furthermore, many programs, when executed, exhibit more complicated, hard to predict memory reference patterns. As such, the useful operation of conventional prefetchers is limited.